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Microchip Introduces DRAM Controller for OpenCAPI Memory Interface

2020-07-14 05:04:25 Technology


With the introduction of the SMC 1000 8x25G serial memory controller, Microchip's subsidiary Microsemi is entering a new market. This is a DDR4 DRAM controller connected to the host processor using the OpenCAPI-derived Open Memory Interface (OMI), a high-speed differential serial link running at 25Gbps per channel. The goal is to connect DRAM through a serial link, enabling the server to scale to a lower number of pins than a traditional parallel DDR interface, resulting in higher memory capacity.

OpenCAPI is one of several competing high-speed interconnect standards designed to go beyond the performance and feature set of PCI Express. The first two CAPI standards were built on top of PCIe 3.0 and 4.0 and provide a low latency, cache-consistent protocol. Version 3 gained Open-prefix by moving the specification from IBM to the new federation, and OpenCapi 3.0 abandoned the base of PCIe and switched to a new 25Gbps link. A subset of OpenCapi 3.1, known as the Open Memory Interface, provides a media-independent low latency protocol for accessing memory. There is an open IP for the host or target that can be used to implement this interface, and an ever-growing ecosystem of business tools for design verification.

The Microchip SMC 1000 8x25G is unsurprisingly connected to the host using an 8-channel open memory interface, and on the downstream side, it has a single-channel DDR4-3200 controller with ECC and supports four levels of memory. At the heart of the SMC 1000 is SERDES, with some additional features that allow the CPU to use an 84-pin connection instead of a 288-pin DIMM interface without sacrificing bandwidth and only generating an additional 4ns delay compared to the attached LRDIMM. Memory controller. The chip itself is packaged in a 17x17 mm package and typically consumes less than 1.7W, supporting dynamic drops to four or two channels on the OMI link to save power when all 25GB/s bandwidth is not required.

On the host side, the first platform to support the open memory interface will be IBM's POWER9 processor, which is expected to announce more details at the OpenPower summit later this month. From an IBM perspective, supporting open memory interfaces allows them to include more memory channels on the same sized chip and provides forward-compatible upgrade paths to DDR5 and NVDIMM or other memory technologies, as the details of these interfaces are now processed on the DDIMM.

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